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SandeepGorrepati/README.md

Hi, I'm Sandeep Gorrepati

Entry-Level Design Verification Engineer | SystemVerilog · UVM · SVA · Formal · cocotb

2025 ECE graduate building and verifying digital hardware. My strongest work is in protocol verification, self-checking testbenches, assertion-based verification, functional coverage, formal property checking, RTL debug, and CPU microarchitecture.

Bengaluru, India · open to relocation across India, Singapore, Malaysia and Taiwan
LinkedIn · sandeep2gvn@gmail.com

Flagship engineering work

Project Engineering proof Reproducible result
AXI4-Lite UVM Verification UVM agent, sequences, driver, monitor, reference-model scoreboard, coverage, SVA and formal response-policy proofs Self-checking regressions, bug injection and committed proof logs
RV32I 5-Stage Pipelined Core Pipeline RTL, forwarding, load-use stalls, branch flushing and reference-model instruction tests 14/14 self-checking instruction tests pass; real branch-decode bug found and fixed
AI MAC-Array Verification Signed 4×4 MAC matrix engine, saturation/overflow checking and independent Python model Directed corners plus constrained-random tests and coverage closure
SPI Master cocotb Verification Python slave BFM, scoreboard and all CPOL/CPHA combinations 48 self-checked transfers, 0 mismatches
DDR Controller Verification Simplified memory-controller verification with self-checking transaction and data-integrity tests Runnable regression evidence; educational controller scope documented in the repository
AXI4-Lite to PCIe-Style Bridge Educational AXI4-Lite-to-packet-interface RTL and FSM verification Protocol-translation demonstration; not a PCIe-compliant implementation

Technical stack

  • Verification: UVM, constrained-random stimulus, functional coverage, SVA, reference-model scoreboards, regression automation, bug injection
  • Formal: SymbiYosys, Z3 and k-induction
  • RTL and architecture: SystemVerilog, Verilog, RV32I pipelines, FSMs, AXI4-Lite, APB and SPI
  • Automation: Python, cocotb, Make, GitHub Actions and Linux
  • Open-source flows: Icarus Verilog, Verilator, Yosys, OpenSTA and OpenROAD

Commercial simulator names are not presented as hands-on experience; the repositories focus on reproducible methodology using accessible tools.

What I can discuss in an interview

  • Root-causing an RV32I branch funct3 decode defect from a failing self-checking test
  • Designing AXI4-Lite monitors, response prediction, SVA and formal properties
  • Closing functional-coverage gaps with directed tests
  • Verifying signed arithmetic, saturation and pipeline latency in a MAC array
  • Building protocol BFMs and reference models in SystemVerilog and Python

Current target

Entry-level Design Verification, Pre-Silicon Verification, RTL/Digital Design, Emulation or hardware-heavy Validation roles.

Pinned Loading

  1. axi4lite-uvm-verification axi4lite-uvm-verification Public

    Full UVM verification environment for an AXI4-Lite slave: agent, reference-model scoreboard, covergroups, and concurrent SVA protocol checks.

    SystemVerilog

  2. rv32i-5stage-pipelined-core rv32i-5stage-pipelined-core Public

    5-stage RV32I pipelined processor in SystemVerilog with forwarding, stalling, and hazard detection.

    SystemVerilog

  3. apb-regfile-cocotb apb-regfile-cocotb Public

    AMBA APB4 register-file slave verified with cocotb: BFM, reference-model scoreboard, functional coverage, PSLVERR error paths. 300 constrained-random transactions, 0 mismatches, 100% coverage; CI.

    Python

  4. dft-scan-atpg dft-scan-atpg Public

    Full-scan insertion + a from-scratch stuck-at ATPG and fault simulator. 100% testable fault coverage, 9 patterns, 0 redundant. Verilog + Python, runs on Icarus.

    Python

  5. rtl-to-gdsii-openroad-flow rtl-to-gdsii-openroad-flow Public

    Exploration of the RTL to GDSII digital ASIC design flow using Verilog, Yosys, OpenROAD, and Sky130 tools.

    Verilog

  6. spi-master-cocotb spi-master-cocotb Public

    SPI master (all 4 CPOL/CPHA modes) verified with cocotb: slave BFM, scoreboard, functional coverage. 48 self-checked transfers, 0 mismatches, 100% coverage; GitHub Actions CI.

    Python